International Business Machines Corporation announced on June 25 what it described as the world’s first sub-nanometer chip technology, advancing transistor scaling to a 0.7-nanometer (7-angstrom) node and pushing the semiconductor industry toward what executives called the “atomic-scale era.”
The company unveiled the breakthrough at its Yorktown Heights research facility in New York, ahead of presentations scheduled for the VLSI Symposium 2026. The chip is built on a new transistor architecture IBM has named Nanostack, which the company describes as the first known three-dimensional design based on nanosheet technology. Nanosheets, also pioneered by IBM, are the foundation of current 3-nanometer and 2-nanometer chips manufactured by leading foundries.
According to IBM, the new process integrates close to 100 billion transistors onto a die roughly the size of a fingernail, approximately double the density of the 2-nanometer chip the company introduced in 2021. Compared with that earlier node, the new technology is projected to deliver performance gains of up to 50 percent, or alternatively up to 70 percent improvement in energy efficiency. Research presented at the VLSI 2026 symposium also indicates the architecture enables a 40 percent reduction in SRAM cell area, which IBM characterised as the largest single-generation step in static memory scaling in more than a decade.
In a statement accompanying the announcement, Jay Gambetta, director of IBM Research, described the development as a milestone moment for computing that takes semiconductor technology from the nanometer era into the atomic scale. With the Nanostack architecture, he added, the company is not merely producing smaller transistors but rethinking how chips are constructed to deliver greater performance and efficiency.
Nanostack works by stacking two complete transistors—one n-type and one p-type—vertically, with each fabricated on a separate wafer and joined through an ultra-thin dielectric bonding layer kept below 30 nanometers thick to minimise capacitive loss. The upper and lower devices can use different channel materials, dielectric stacks and threshold voltages, allowing each layer to be tuned independently for performance and power. According to figures disclosed by IBM, each nanosheet is roughly 5 nanometers tall—about the width of 15 silicon atoms—while the spacing between the upper and lower transistor sets is around 9 nanometers.
The “0.7-nanometer” label refers to a generational node name rather than a physical gate length, in line with industry naming conventions that have long decoupled node designations from actual transistor dimensions. IBM said laboratory demonstration silicon has validated three engineering milestones: ultra-thin dielectric bonding for CMOS integration, dual-channel material engineering with independently tunable upper and lower devices, and the expected switching behaviour of CMOS inverter circuits built on the new architecture.
The company said Nanostack could enter volume production within five years, suggesting a possible commercial timeline around 2031. IBM has previously licensed elements of its semiconductor research to South Korea’s Samsung Electronics and Japan’s Rapidus Corporation, which is collaborating with IBM on commercialising 2-nanometer production. A manufacturing partner for the Nanostack process has not yet been identified.
Shares in IBM rose more than 6 percent in U.S. pre-market trading on June 25 following the announcement. Industry observers noted that scaling Nanostack to volume production will require advanced equipment such as High-NA extreme ultraviolet lithography from Dutch supplier ASML, alongside mature angstrom-scale yield control and a full electronic design automation tool chain.
The semiconductor industry has spent much of the past decade debating whether traditional Moore-style scaling can continue beyond the 1-nanometer threshold. IBM said Nanostack offers evidence that further density and efficiency gains remain achievable. The architecture is intended to support workloads including generative artificial intelligence, cloud infrastructure and next-generation consumer electronics, segments where rising demand for compute power and lower energy consumption has put pressure on chip designers to extend scaling.
