Researchers at the University of Illinois Urbana-Champaign have demonstrated a breakthrough in monolithic 3D integration of silicon electronics, potentially extending Moore’s Law for years to come.
The study, published in Nature on May 27, 2026 (DOI: 10.1038/s41586-026-10496-6), was led by Professor Qing Cao and his team at the Grainger College of Engineering. The research received support from industry partners including IBM, Intel, and TSMC.
The key innovation lies in the ability to stack multiple layers of silicon electronic devices directly on top of each other using ultra-thin silicon nanomembranes measuring less than 10 nanometers in thickness. The team developed a low-temperature transfer process operating below 200 degrees Celsius, which prevents damage to underlying circuits.
To overcome the thermal limitations of traditional doping processes, the researchers employed junctionless transistor designs. In their demonstration, they successfully fabricated three-layer stacks containing 625 transistors per layer, achieving yields between 98 and 100 percent.
The output current density of these stacked devices matched that of conventional transistors manufactured on bulk silicon wafers. Performance metrics showed 3-4 times improvement compared to monolithic devices built with alternative materials.
The team successfully demonstrated both 3D logic circuits and SRAM memory cells. According to the researchers, the process is scalable beyond three layers, though further development is needed before commercial implementation.
The next step involves transferring the technology to industrial semiconductor foundries. Industry observers note that if successfully scaled, this approach could enable continued miniaturization and performance improvements in microelectronics.
The research represents a significant advancement in the field of advanced semiconductor manufacturing, though commercial applications remain years away from widespread deployment.